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august 2008 rev 1 1/36 AN2816 application note high-efficiency step-down controller with embedded 2 a ldo regulator introduction the pm6675s device consists of a single, high-efficiency step-down controller and an independent low dropout (ldo) linear regulator. the constant on-time (cot) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. an embedded integrator control loop compensates the dc voltage error due to the output ripple. selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. the low-noise mode sets the minimum switching frequency to 33 khz for audio- sensitive applications. the ldo linear regulator can sink and source up to 2 apk. two fixed current limits (1 a and 2 a) can be chosen. an active soft-end is independently performed on both the switching and the linear regulators outputs when disabled. figure 1. pm6675s demonstration board am01000v1 www.st.com
contents AN2816 2/36 contents 1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 switching section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 ldo section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 evaluation kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 jp3 fixed or adjustable output voltage (vsel pin) . . . . . . . . . . . . . . . . . . 14 7.2 jp1 power-saving mode (noskip pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 jp2 current limit (lilim pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 jp5 compensation network (comp pin) . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 pm6675s demonstration tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.1 v out and l out turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.2 v out working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 v out and l out load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.4 v out and l out load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.5 v out efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.6 v out gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.7 v out and l out turn-off (soft-end) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.8 uv, ov and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AN2816 contents 3/36 10.9 v out current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.10 l out current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.11 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of figures AN2816 4/36 list of figures figure 1. pm6675s demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pm6675s demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. jp3 (vsel) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. jp1 (noskip) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. jp2 (lilim) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. jp5 (comp) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. pm6675s demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. vout soft-start at 270 mw load, pulse-skip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. l out turn-on, v out in pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. v out = 1.5 v, v in = 12 v, i vout = 0 a, forced-pwm mode . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. v out = 1.5 v, v in = 12 v, i vout = 0 a, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. v out = 1.5 v, v in = 12 v, no load, non-audible pulse-skip mode (33 khz) . . . . . . . . . . . . 23 figure 19. v out load regulation - v in = 12 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20. l out load regulation - ldoin = 1.5 (v out ), he dropout voltage (0.35 v) limits the maximum sourced current to about 1.8 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. v out load transient (v in = 12 v, load = 0 a to 8 a at 2.5 a/s), pulse-skip mode. . . . . . 25 figure 22. v out load transient (v in = 12 v, load = 8 a to 0 a at 2.5 a/s), pulse-skip mode. . . . . . 25 figure 23. l out load transient (v in = 12 v, load = 1.8 a to 1.85 a at 2.5 a/s), pulse-skip mode . . 25 figure 24. forced pwm (blue), non-audible pulse-skip (green), pulse-skip (red), efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 25. external mosfet gate signals (v in = 12 v, load = 0), pulse-skip mode . . . . . . . . . . . . 27 figure 26. external mosfet gate signals (v in = 12 v, load = 7 a), pulse-skip mode . . . . . . . . . . 27 figure 27. v out and l out output voltages v out soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 28. v out and l out output voltages, l out soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 29. uv protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 30. ov protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 31. v out and l out rails, thermal shutdown, pulse-skip mode, l out powered by v out . . . . . 31 figure 32. v out current limit protection during a load transient (0 a to 9 a at 2.5 a/s, valley current limit programmed at about 9 a (r ilim = 1 kw) pulse-skip mode. . . . . . . . . . . . . . . . . . . . . 32 figure 33. l out current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 34. switching frequency vs. input voltage, v out = 1.5 v, i vout = 7 a, forced pwm mode . . . 34 figure 35. switching frequency vs. output current, v out = 1.5 v, v in = 12 v . . . . . . . . . . . . . . . . . . . 34
AN2816 main features 5/36 1 main features 1.1 switching section 4.5 v to 28 v input voltage range 0.6 v, 1% voltage reference 1.5 v fixed output voltage 0.6 v to 3.3 v adjustable output voltage 1.237 v 1% reference voltage available very fast load transient response constant on-time loop control no-r sense current sensing using low-side mosfets' r ds(on) negative current limit latched ovp, uvp and thermal shutdown fixed 3 ms soft-start selectable pulse-skip ping at light load selectable non-audible (33 khz) pulse-skip mode all ceramic output capacitor applications supported output voltage ripple compensation output soft-end 1.2 ldo section 0.6 v to 3.3 v adjustable output voltage selectable 1 a or 2 a current limit dedicated power good signal ceramic output capacitors supported output soft-end
evaluation kit schematic AN2816 6/36 2 evaluation kit schematic figure 2. pm6675s demonstration board schematic am01001v1 0 0 j2 vout 1 j3 pgnd 1 j9 pgnd 1 j1 vin 1 j5 vcc 1 jp3 vsel 0 0 0 u1 pm6675s lout 24 lin 23 boot 22 hgate 21 phase 20 csns 19 vcc 18 lgate 17 pgnd 16 spg 15 len 14 swen 13 lilim 12 comp 11 vsel 10 vsns 9 vosc 8 vref 7 avcc 6 sgnd 5 lpg 4 noskip 3 lfb 2 lgnd 1 thpd 25 j10 vccgnd 1 q2 s12nh3ll 5 4 1 6 7 8 2 3 q1 s12nh3ll 5 4 1 6 7 8 2 3 j11 lgnd 1 j6 lin 1 2x umk325bj106km-t r19 7.5k r20 10k d1 bat54j 2 1 r4 3r3 1 2 0 r3 1.2k 1 2 r1 330k 1 2 r2 18k 1 2 l1 0.9u 1 2 d2 2 1 c21 100p 1 2 c1 10u 1 2 c2 10u 1 2 c3 220u 1 2 c4 220u 1 2 c10 1 2 c9 100n 1 2 c22 100p 1 2 r7 3r9 1 2 0 c19 n.m. 1 2 0 c13 100n 1 2 c20 n.m. 1 2 sw1 1 2 4 3 r11 100k 1 2 r12 100k 1 2 r18 100k 0 0 vcc r14 7.5k r15 6.8k c15 6.8n 1 2 c16 680p 1 2 c17 n.m. 1 2 c6 10u 1 2 r17 0 vcc vcc vcc vcc c11 10u 1 2 c14 100n 1 2 tp1 gnd_tp j4 spg 1 r13 100k 1 2 0 c5 1u 1 2 jp5 int-vesr jp2 lilim 1 2 3 4 5 6 jp1 noskip 1 2 3 4 5 6 d3 stps1l30a 2 1 0 0 c7 10u 1 2 0 0 r8 12k r9 13k r6 0 stps1l30m r10 0 mlc 1240-901ml 2x 4tpe220mf c12 100n 1 2 len-swen j7 lout 1 j8 lpg 1 c18 1n 1 2 r16 4r7 0 0
AN2816 bill of material 7/36 3 bill of material table 1. pm6675s demonstration board bill of material qty component description package part number manufacturer value 2 c1, c2 ceramic, 50 v, x5r, 20% smd 1210 umk325bj106k m-t taiyo yuden 10 f 2 c3, c4 poscap, 4 v,15 m ? , 20% smd 7343 (d) 4tpe220mf sanyo 220 f 1 c5 ceramic, 6.3 v, x5r, 10% smd 3216-12 standard 1 f 3 c6, c7, c11 ceramic, 6.3 v, x5r, 10% smd 0805 jmk212bj106k g-t taiyo yuden 10 f 4 c9, c10, c13, c14 ceramic, 50 v, x7r, 20% smd 0603 standard 100 nf 1 c12 ceramic, 50 v, x7r, 10% smd 0805 standard 100 nf 1 c15 ceramic, 50 v, x7r, 10% smd 0603 standard 6n8 1 c16 ceramic, 50 v, x7r, 10% smd 0603 standard 680 p 1c17 ceramic, 20% smd 0603 standard n.m 1 c18 ceramic, 50 v , x7r, 10% smd 0805 standard 1 nf 2 c19, c20 ceramic, 6.3 v, x5r, 10% smd 0805 jmk212bj106k g-t taiyo yuden n.m 2 c21, c22 ceramic, 50 v, x7r, 10% smd 0603 standard 100 pf 1 r1 chip resistor, 0.1 w, 1% smd 0603 standard 300 k ? 1 r2 chip resistor, 0.1 w, 1% smd 0603 standard 18 k ? 1 r3 chip resistor, 0.1 w, 1% smd 0603 standard 1.2 k ? 1 r4 chip resistor, 0.1 w, 1% smd 0603 standard 3r3 1 r6 chip resistor, 0.1 w, 1% smd 0805 standard 0 1 r7 chip resistor, 0.1 w, 1% smd 0603 standard 3r9 1 r8 chip resistor, 0.1 w, 1% smd 0603 standard 12 k ?
bill of material AN2816 8/36 1 r9 chip resistor, 0.1 w, 1% smd 0603 standard 13 k ? 1 r10 chip resistor, 0.1 w, 1% smd 0603 standard 0 4 r11, r12, r13,r18 chip resistor, 0.1 w, 1% smd 0603 standard 100 k ? 2 r14, r15 chip resistor, 0.1 w, 1% smd 0805 standard n.m 1 r16 chip resistor, 0.1 w, 1% smd 0805 standard 4r7 1 r17 chip resistor, 0.1 w, 1% smd 0603 standard 0 1 r19 chip resistor, 0.1 w, 1% smd 0603 standard 7k5 1 r20 chip resistor, 0.1 w, 1% smd 0603 standard 10 k ? 1 l1 smt, 13.4 arms, 2.57 m ? 10.5x10.5 mm mlc1240- 901mx coilcraft 0.9 h 2 q1, q2 n-channel, 30 v so-8 sts12nh3ll stmicroelectronics sts12nh3ll 1 d1 schottky, 30 v, 0.3 a sod-323 bat54j stmicroelectronics bat54j 1 d2 schottky, 30 v, 1 a do216- aa stps1l30m stmicroelectronics stps1l30m 1 d3 schottky, 30 v, 1 a do216- aa stps1l30m stmicroelectronics n.m. 1 u1 controller vfqfpn- 24 pm6675s stmicroelectronics pm6675s 11 j1, j2, j3, j4, j5, j6, j7, j8, j9, j10,j11 header, single pin 3 jp1, jp2, jp3 jumper, 2x3, 100 mils 1 jp5 pcb pads selector 1 tp6 test point 1 sw1 dip switch 2 dip-2 standard table 1. pm6675s demonstration board bill of material (continued) qty component description package part number manufacturer value
AN2816 component assembly and layout 9/36 4 component assembly and layout figure 3. top side component placement figure 4. top view am01002v1 am0100 3 v1
component assembly and layout AN2816 10/36 figure 5. layer 2 view figure 6. layer 3 view am01004v1 am01005v1
AN2816 component assembly and layout 11/36 figure 7. bottom view figure 8. bottom side component placement am01006v1 am01007v1
i/o interface AN2816 12/36 5 i/o interface the pm6675s demonstration board has the following test points as shown in ta b l e 2 . table 2. pm6675s demonstration board input and output interface test point description v in battery input voltage positive terminal v out switching regulator output pgnd battery input and v out output common return l in ldo linear regulator input l out ldo linear regulator output lgnd ldo linear regulator output return lpg ldo linear regulator power good signal vcc +5 v supply, positive terminal vccgnd signal ground and vcc supply return spg v out sw regulator power good signal tp1 connection point between power and signal grounds
AN2816 recommended equipment 13/36 6 recommended equipment 4 v to 28 v, 30 w power supply active loads digital mutimeters 200 mhz four-trace oscilloscope
configuration AN2816 14/36 7 configuration the pm6675s demonstration board allows the user to choose the desired mode of operation using four jumpers (jp1, jp2, jp3 and jp5) and two resistors. refer to the following configuration description. 7.1 jp3 fixed or adjustable output voltage (vsel pin) the jp3 jumper is used to choose between fixed output voltage (1.5 v) and a user-defined output voltage in the range 0.6 v to 3.3 v. when connected in the lower position, the fixed 1.5 v output voltage is selected ( figure 9 ). if jp3 is in the upper position, the output voltage is given by: equation 1 the r8 and r9 resistors are set to 12 k ? and 13 k ? respectively (1.25 v output voltage) and can be changed by the user. 7.2 jp1 power-saving mode (noskip pin) the jp1 jumper allows choosing the mode of operation of the switching section. three options (forced-pwm, pulse-skip and non-audib le pulse-skip) can be selected by changing the jp1 setting as shown in figure 10 : figure 9. jp3 (vsel) setting 8 r 9 r 8 r 6 . 0 vout adj + ? = !-v 6 fixedoutput voltage defaultposition !djustableoutputvoltage
AN2816 configuration 15/36 7.3 jp2 current limit (lilim pin) the jp2 jumper is used to select the ldo curr ent limit. in the upper position the ldo output current limit is set to 2 a, while in the lower position the current limit is set to 1 a. the middle position is not used. figure 10. jp1 (noskip) setting !-v .oaudiblepulse skip &orced07- defaultposition 0ulse skip figure 11. jp2 (lilim) setting !-v !,$/currentlimit !,$/currentlimit
configuration AN2816 16/36 7.4 jp5 compensation network (comp pin) the jp5 jumper is located on the bottom side of the pm6675s board and allows connecting the integrator input (comp pin) to the output through a simple capacitor (integrative compensation) or using the "virtual esr" network for very low esr output capacitor applications (e.g. all ceramic output cap applications). the integrative compensation is set by default. refer to the pm6675s datashee t for details about the all-ceramic output capacitor applications and the virtual esr design. figure 12. jp5 (comp) setting !-v 6irtual %32network )ntegrativecompensation defaultposition
AN2816 test setup 17/36 8 test setup figure 13 shows the suggested setup connecti ons between the pm6675s demonstration board, the loads and the external supply. the ldo input (lin) is connected to v out by default (r6 = 0 ? ). figure 13. pm6675s demonstration board test setup am01012v1
getting started AN2816 18/36 9 getting started the following step-by-step power-up and power-down sequences are provided in order to correctly evaluate the pm6675s demonstration board performance. power-up sequence ? working in an esd-protected environment is highly recommended. check all wrist straps and ground mat connections bef ore handling the pm6675s demonstration board ? connect power supplies as shown in the pm6675s demonstration board test setup ( figure 13 ) and insert the meters in order to perform the desired performance evaluation. connect the scope-probes as desired ? set the jp1 through jp5 jumpers in order to properly configure the pm6675s board (default position suggested). set the swen-len switches to the on position (upper position). do not change jumper settings when the board is powered ? set the v cc supply to 5 v5% and the current limit to 100 ma ?set the v in supply to a voltage in the range 4.5 v to 28 v. an initial test at 12 v and 3 a current limit is suggested ? set all the loads to 0 a ? turn-on the v in supply ? turn-on the v cc supply ?vary the v out load from 0 a to 10 a ?vary the l out load from 0 a to 2 a to test sour ce capability. if a different ldo input is desired, connect the external rail as dashed in figure 13 and remove the r6 resistor. all changes must be don e when the board is not powered ?vary v in supply from 4.5 v to 28 v power-down sequence ? decrease l out loads to 0 a ? reduce v out load to 5 a ? decrease v cc supply from 5 v to 3.8 v in order to test the uvlo ? increase v cc supply from 3.8 v to 5 v to restart the device ? use the swen-len switches to test so ft-start and soft-end on both outputs ? turn-off the v out load ? turn-off the v cc supply ? turn-off the v in supply
AN2816 pm6675s demonstration tests 19/36 10 pm6675s demonstration tests 10.1 v out and l out turn-on (soft-start) the v out soft-start is divided in 4 steps. in each step the current limit is increased by ? of the nominal value. this behavior is well understood by loading the rail, as performed in the test. l out soft-start is performed at its maximum available current. figure 14. v out soft-start at 270 m ? load, pulse-skip mode am0101 3 v1
pm6675s demonstration tests AN2816 20/36 figure 15. l out turn-on, v out in pulse-skip mode am01014v1
AN2816 pm6675s demonstration tests 21/36 10.2 v out working mode v out forced pwm mode when the forced pwm working mode is select ed (jp1 in the upper position), the inductor current is allowed to become negative and the following waveform can be captured. figure 16. v out = 1.5 v, v in = 12 v, i vout = 0 a, forced-pwm mode am01015v1
pm6675s demonstration tests AN2816 22/36 v out pulse-skip mode the default working mode is the pulse-skip algorithm, in which the low-side mosfet is turned off when the inductor current becomes equal to zero. this behavior allows reaching the maximum efficiency. figure 17. v out = 1.5 v, v in = 12 v, i vout = 0 a, pulse-skip mode am01016v1
AN2816 pm6675s demonstration tests 23/36 v out non-audible pulse-skip mode in order to avoid too low switching frequencies, the non-audible pulse-skip mode can be selected (jp1 in the middle). doing so, the minimum switching frequency allowed is 33 khz as depicted in figure 18 . figure 18. v out = 1.5 v, v in = 12 v, no load, non-audible pulse-skip mode (33 khz) am01017v1
pm6675s demonstration tests AN2816 24/36 10.3 v out and l out load regulation figure 19 and 20 refer to v out and l out output voltage variations versus load current. the switching section directly supplies the linear ldo. figure 19. v out load regulation - v in = 12 v figure 20. l out load regulation - ldoin = 1.5 (v out) , he dropout voltage (0.35 v) limits the maximum sourced current to about 1.8 a am0101 8 v1 1.5 v lo a d reg u l a tion 1.48 1.49 1.50 1.51 1.52 1.53 1.54 o u tp u t c u rrent [a] o u tp u t volt a ge [v] pwm no au d. s kip s kip 0.1 0.10 1.00 10.00 !-v ,/54loadregulationvsloadcurrent #urrent;!= ,/54;6= #,! #,!
AN2816 pm6675s demonstration tests 25/36 10.4 v out and l out load transient responses load transient responses are evaluated by loading v out and l out output rails with a current slew rate of 2.5 a/s. in this test the switching section v out works in pulse-skip mode and directly supp lies the linear regulator. figure 21. v out load transient (v in = 12 v, load = 0 a to 8 a at 2.5 a/ s), pulse-skip mode figure 22. v out load transient (v in = 12 v, load = 8 a to 0 a at 2.5 a/ s), pulse-skip mode am01020v1 am01021v1 figure 23. l out load transient (v in = 12 v, load = 1.8 a to 1.85 a at 2.5 a/s), pulse-skip mode am01022v1
pm6675s demonstration tests AN2816 26/36 10.5 v out efficiency the three working modes lead to different power efficiency. the test setup is v in =12 v, fsw=330 khz, v out =1.5 v. figure 24 summarizes the results. figure 24. forced pwm (blue), non-audible pulse-skip (green), pulse-skip (red), efficiency vs. output current !-v %fficiencyvsload6out66in6 /utputcurrent! %fficiency &orced07- .o audible0 3 0ulse skip
AN2816 pm6675s demonstration tests 27/36 10.6 v out gate drivers the pm6675s power mosfet driver turns on and off the high-side and low-side external mosfets, avoiding cross-conduction. in the following two pictures the gates signals are shown in two different load conditions: without load ( figure 25 ) and with load ( figure 26 ). figure 25. external mosfet gate signals (v in = 12 v, load = 0), pulse-skip mode figure 26. external mosfet gate signals (v in = 12 v, load = 7 a), pulse-skip mode am01024v1 am01025v1
pm6675s demonstration tests AN2816 28/36 10.7 v out and l out turn-off (soft-end) v out soft-end when the swen pin is pulled down, the swit ching section performs the output capacitor discharge by turning on the discharge mosfet. the external low-side mosfet is turned on when the output voltage is lower than about 400 mv. figure 27. v out and l out output voltages v out soft-end am01026v1
AN2816 pm6675s demonstration tests 29/36 l out soft-end by pulling down the len pin the linear regulator is forced to discharge its output capacitor, by turning on its discharge mosfet. doing so, the l out rail is turned off in a safe way, avoiding output voltage under ground spikes. figure 28. v out and l out output voltages, l out soft-end table 3. typical discharge mosfets r ds(on) resistance description v out output l out output typical discharge mosfets r ds(on) 25 ? 25 ? am01027v1
pm6675s demonstration tests AN2816 30/36 10.8 uv, ov and thermal protections latched uv protection if the switching section output voltage is lower than the 70% nominal value, the undervoltage state is entered and the discharge mosfet is turned on (as in the the soft-end state). figure 29. uv protection, pulse-skip mode am0102 8 v1
AN2816 pm6675s demonstration tests 31/36 latched ov protection if the switching section output voltage is higher than the 115% nominal value, the overvoltage state is entered and the low-side mosfet is turned on in order to quickly discharge the output capacitor and avoid load damages. latched thermal shutdown if the junction temperature rises above 150 deg, the thermal protection circuit turns off the device and discharges the switching section ou tput capacitor by performing the soft-end. figure 30. ov protection, pulse-skip mode figure 31. v out and l out rails, thermal shutdown, pulse-skip mode, l out powered by v out am01029v1 am010 3 0v1
pm6675s demonstration tests AN2816 32/36 10.9 v out current limit the valley current limit avoids any high-side turn -on if the inductor current is higher than the programmed value. this current limit can be designed with the following equation: equation 2 the current sensing is performed by comparing the voltage drop in the low-side mosfet, during the toff period, with the voltage drop given by an injected current and the current limit resistor. figure 32. v out current limit protection during a load transient (0 a to 9 a at 2.5 a/ s, valley current limit programmed at about 9 a (r ilim = 1 k ? ) pulse-skip mode i cl 100 ar ilim ? r ls ds on () , ------------------------------------ - = am010 3 1v1
AN2816 pm6675s demonstration tests 33/36 10.10 l out current limit (foldback) the linear ldo regulator has a fo ldback protection feature which reduces the current limit to about 1 a when the output voltage is outside the 10% power good window. the current limit is restored to about 2 a when the output voltage re-enters the power good window. if the ldo programmed current limit is 1 a, wh en the output voltage is outside the 10% power good window, the short circuit current is about 500 ma. figure 33. l out current limit during an output short am010 3 2v1
pm6675s demonstration tests AN2816 34/36 10.11 switching frequency switching frequency vs. input voltage the constant on-time controller leads to a q uasi-constant switchin g frequency, slightly following the input voltage. switching frequency vs. output current the switching frequency can decrease to very low values in pulse-sk ip mode but in non- audible pulse-skip there is a lo wer limit (about 33 khz). by increasing the load, however, the switching frequency increases a bit, as a co nsequence of conduction and switching losses. figure 34. switching frequency vs. input voltage, v out = 1.5 v, i vout = 7 a, forced pwm mode figure 35. switching frequency vs. output current, v out = 1.5 v, v in = 12 v am010 33 v1 1.5 v s witching fre qu ency v s inp u t volt a ge 250 3 00 3 50 400 450 500 550 600 inp u t volt a ge [v] f s w [khz] pwm @ 0 a pwm @ 7 a 0 5 10 15 20 25 3 0 am010 3 4v1 s witching fre qu ency v s lo a d c u rrent 0 100 200 3 00 400 500 600 0.01 0.1 1 10 o u tp u t c u rrent [a] f s w [khz] p u l s e s kip no au d. s kip pwm
AN2816 revision history 35/36 11 revision history table 4. document revision history date revision changes 20-aug-2008 1 initial release
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